Job Description

Enterprise Select has partnered with a revolutionary Biotech company in the Bay Area to help build out their cutting-edge Engineering team. As a Senior FPGA Design Engineer, you will be responsible for all facets of the verification of FPGS designs as well as assist in the verification of ASIC designs. You will also help with other aspects of design verification, including front-end architecture planning, system modeling, external IP integration verification, flow development, and EDA tool evaluation and selection.


  • Ownership of all aspects of the design verification of the FPGA chips and its functional blocks
  • Test Plan ownership, and coordination with Architecture, Design, DFT, and other teams to deliver a complete, comprehensive verification plan
  • Ownership of system, chip, and IP models for verification
  • Evaluation and selection of flows and EDA tools
  • Development and deployment of processes and flows for Design Verification


  • A Master or BS degree with 8+ years of industry experience in FPGA / ASIC design verification
  • Hands-on experience in the entire verification process, from test plan to block and system level simulation, using standard EDA tools (Cadence Incisive suite and/or Mentor Questa)
  • Hands-on experience with Block level and System level tests writing for FPGA / ASIC designs
  • Knowledge of code coverage methodology
  • Experience with UVM and related verification methodologies and tools
  • Domain expertise in standard bus protocols: PCIe, SPI, I2C, LVDS
  • FPGA-based co-simulation, and emulation platforms for Design Verification
  • Knowledge of:
  • SystemVerilog & Object-Oriented techniques
  • Scripting languages such as Python, Perl, Shell
  • Solid debugging and problem-solving skills


This is an urgent position with an immediate need to hire. If you meet the qualifications above and are interested in pursuing this opportunity, get in touch with us today for immediate consideration!


Application Instructions

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